linux VHDL : to_bitvector + compiling problem

[gjffghf]

"Nikiforakis Manos" <nmano at skiathos.physics.auth.gr> wrote :


Hello,

> [snip]
>...
> [/snip]
>
>Meta apo ligo psaximo, eida pws ta sfalmata auta exoun sxesh me thn entolh
>to_bitvector h opoia xrhsimopoieitai 3 fores sto programma (test.vhdl) stis
>grammes 31, 33, 35.
>
>Kammia idea?

xmmmmmm 3anakoitas to Install-Notes gia to poia ekdosi C++ compiler
apaiteitai
gia to simulation, merikes fores einai arketo afto gia na trabas ta
mallia sou mexri na ginoun rasta.....

>Mou eipes an de kanw la8os, pws xrhsimopoieis to Ver(ilog) etsi? Poia
>biblio8hkh ths GTK xreiazetai gia na egkatasta8ei? Kai yparxei kapoio arxeio
>me odhgies egkatastaseis -giati den brhka pou8ena kati tetoio. ?

GTK ???
( damn, i ego exo meinei poli piso , i allo verilog prospa8eis na kaneis
egatastasi )

sto linux den 3ero ti apaitiseis exei , kato apo NetBSD pantos den
anaferei pou8ena
dependecies gia GTK.

Verilog Home Page:
http://icarus.com/eda/verilog/index.html


BTW ri3e mia matia sto Alliance :
http://www-asim.lip6.fr/alliance/
Mou exoun pei oti einai apo ta kalitera VHDL-tools , den to exo
dokimasei akoma vevaia

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