the ++ operator

[Aggelos Economopoulos]

On Sunday 23 November 2003 13:10, Manolis Stamatogiannakis wrote:
> On Sun, 23 Nov 2003, Aggelos Economopoulos wrote:
> > On Saturday 22 November 2003 14:36, Manolis Stamatogiannakis wrote:
> > [snip]
> >
> > > Exw thn entypwsh pws mporei na ginei akoma pio grhgoro dhlwnontas thn
> > > metavlhth p san register. Dhladh: register char *p;
> > > To "register" pantws, apotelei hint ston compiler. An o compiler
> > > nomizei pws tou 'perisevoun' registers, 8a afierwsei ena register gia
> > > na krataei thn timh tou p. Alloiwtika to p 8a meinei aplh metavlhth kai
> > > h taxythta 8a meinei h idia.
> >
> > Oi shmerinoi compilers agnooun to 'register' hint (kai me to dikio
> > tous...). Sthn periptwsh tou gcc (apo to info page, 'C Implementation' ->
> > 'Hints implementation'):
>
> Teleutaia fora pou to dokimasa douleue pantws :) Prepei na htan omws
> '97-'98 kai to mhxanhma na htan sparc.
>
> Apo mia matia omws sto online documentation tou gcc, fainetai pws yparxei
> akoma h dynatothta na dhlwseis mia metavlhth sa register mono pou exei
> alla3ei h synta3h. Dhladh pleon prepei na katonomaseis kai ton register
> pou 8eleis na kratietai h metavlhth (Explicit Reg Var [1] - 1h periptwsh
> se auta pou aneferes).

Nai, omws o gcc den sou dinei auth th dunatothta gia na dineis optimization 
hints (to anti8eto malista, ta asm/__asm__ den apokleietai na xeirotereuoun 
to register allocation), alla gia polu sugkekrimenes periptwseis kata th 
xrhsh inline assembly (an kai me ta non-obvious semantics pou exei, sunh8izw 
apla na anoigw ena .S) (ola auta gia local vars bebaia). E3allou, me th xrhsh 
tou asm(), petas to portability sta skoupidia.

[snip]
> Anaferontai epishs sta slides kai pragmata pou einai gnwsta, alla oi
> compilers den prokeitai na peira3oun. Px an exeis ena mikro pinaka mikrwn
> akairewn pou ginetai access poly syxna kai kaneis thn koutoponhrh epilogh
> na ton dhlwseis 'short int', kerdizeis merika (f8hna shmera) bytes mnhmhs,
> omws xaneis para poly se apodwsh e3aitias tou oti oi shorts den einai
> 32bit alligned.

Apo to intel architecture optimization manual (memory accesses -> alignment)

For best performance, align data as follows:
[...]
Align 16-bit data to be contained within an aligned four byte word.

Oso gia ta 'f8hna bytes', 8umhsou oti ta L? bytes den einai _ka8olou_ fthna, 
kai dedomenou oti h ram einai polu pio argh apo ton epe3ergasth to na 
meiwseis to mege8os tou array sto miso einai shmantiko kerdos.